V. Jamuna ¹, P. Gomathi ¹, A. Arun ¹

Affiliations
1 Electronics and Communication Engineering, M. Kumarasamy College of Engineering, Karur, Thalavapalayam – 639113, Tamil Nadu, IN

Abstract

Objectives: FIR filter structure is designed with area and delay optimization is designed using Systolic Architecture and Associativity High Level Transformation technique in this paper. Finite Impulse Response (FIR) filter structure with optimized parameters is one of the major challenges in VLSI Signal Processing. Methods/Statistical Analysis: The designed FIR filter is designed using Modelsim for functionality verification and the structure is implemented in Spartan 3E FPGA kit using Xilinx ISE simulator for the analysis of the designed architecture. Findings: The FIR filter is designed with 4-Tap, 8-Tap and 16-Tap length and the designed architecture using Systolic architecture with Associativity technique shows 8.9%, 2.3% and 2.4% reduction in LUT for 4-Tap,8-Tap and 16-Tap filter respectively and 14.22%,11.89% and 12.32% reduction in delay for 4-Tap,8-Tap and 16-Tap filter respectively. Application/Improvements: Further Associativity techniques may be used for future work.

Keywords

Architecture, FIR Filter, High Level Transformation

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S. Tamilselvan ¹, A. Arun ¹

Affiliations
1 Department of Electronics and Communication Engineering, M. Kumarasamy College of Engineering, Karur - 639113, Tamil Nadu, IN

Abstract

Objectives: An efficient MAC design is planned for 2’s complement numbers with no more than partial-product creation methodology and diminution tree, whereas the succeeding step trappings an extraordinary sign-conservatory solutions. Methods/Statistical Analysis: Accumulate operations form an important process in signal and image processing applications. To expand MAC execution, the basic way postponement can be diminished by embeddings an additional pipeline register, either in the interior the two rows or stuck between the twos and the final adder. Findings: The 16 bit MAC architecture is implemented using Baugh-Wooley (BW) multiplier with Twin precision concept. The proposed methodology is verified by implementing in a 16 x 16 MAC unit. The performance parameters extracted demonstrates that the proposed Modified Booth with Twin precision based 16 bit MAC demonstrates an area reduction of 45.3%, delay reduction of 30.8% and power saving of 60% when compared to the MAC architectures designed using Baugh-Wooley with twin precision multiplier. Application/Improvements: It performs better than the conventional MAC in all the aspects.

Keywords

Baugh-Wooley Multiplier, MAC Design, Partial-Product, Sign-Conservatory Solutions, Twin Precision

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